Alberto Embedded & Open experience

In the CPU board there is a 2 Gb NAND Flash chip organized in :

1 Device = (2K+64)Bytes x 64Pages x 2048 Blocks = 2112Mbits

This chip is connected to the i.MX31 Application Processor through the Nand Flash Controller Interface with an 8 bit data bus. The in kernel driver “drivers/mtd/nand/mxc_nand.c” can easily support it registering the nand device in the machine code with the follow platform data:

static struct mxc_nand_platform_data imx31pdk_nand_flash_pdata = {
       .width          = 1, /* 1 Byte data bus */
       .hw_ecc         = 1, /* No suppress hardware ECC */
};

The mxc_nand.c driver is enabled by default with a $ make mx3_defconfig

What can be enabled is the MTD Partitioning support with support for RedBoot partition table parsing where the Location of RedBoot partition table is the number of the Flash page where it is stored the RedBoot “FIS directory” that for me start at 0×80000, so it is the fourth page (4).

The resulting patch:

Subject: [PATCH 2/2] MXC: imx31pdk: Add support for on board NAND Flash.

Signed-off-by: Alberto Panizzo <alberto.panizzo@gmail.com>
---
arch/arm/mach-mx3/mx31pdk.c |   10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
index 0f7a2f0..ca1fe5d 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -34,6 +34,7 @@
#include <mach/board-mx31pdk.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
+#include <mach/mxc_nand.h>
#include "devices.h"

/*!
@@ -53,6 +54,14 @@ static int mx31pdk_pins[] = {
IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
};

+/*
+ * NAND Flash
+ */
+static struct mxc_nand_platform_data imx31pdk_nand_flash_pdata = {
+    .width        = 1,
+    .hw_ecc        = 1,
+};
+
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
@@ -241,6 +250,7 @@ static void __init mxc_board_init(void)
"mx31pdk");

mxc_register_device(&mxc_uart_device0, &uart_pdata);
+    mxc_register_device(&mxc_nand_device, &imx31pdk_nand_flash_pdata);

if (!mx31pdk_init_expio())
platform_device_register(&smsc911x_device);
--
1.6.3.3

On the imx31 PDK CPU board there are mainly those chips:

Application processor:

i.MX31

RAM Memory:

128 MB (1 Gb) DDR

iMX31 EMI

NAND Flash:

256 MB (2 Gb)

iMX31 NFC

Power Management and Audio IC:

MC13783

iMX31 SPI2

USB transceiver:

ISP 1504

iMX31 USB OTG

RAM memory is native managed by the iMX31 External Memory Interface, then the first chip that can be supported is the NAND Flash. Then we must to go through the support for the Power management chip to go ahead with all other devices because MC13783 hold the entire power supply management, with its Regulator interface.

In those days I am involved in supporting the Freescale i.MX PDK developing board in the mainline kernel.

This is not a simple job because there are (at first seeing) a lot of holes in mainline kernel.

Stay tuned for news!